中國有色金屬學(xué)報(bào)(英文版)
Transactions of Nonferrous Metals Society of China
| Vol. 26 No. 6 June 2016 |
（1. School of Materials Science and Engineering, Dalian University of Technology, Dalian 116024, China;
2. Department of Engineering Mechanics, Dalian University of Technology, Dalian 116024, China）
Abstract:To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board (PCB) side, split between redistribution layer (RDL) and Cu under bump metallization (UBM), RDL fracture, bulk cracks and partial bulk and intermetallic compound (IMC) cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
Key words: Sn-3.0Ag-0.5Cu; wafer level chip scale package; solder joint; drop failure mode
